1. Field of the Invention
The present invention relates to a display device for displaying an image using inputted digital video signals. Note that a display device in this specification includes a liquid crystal display device using a liquid crystal element for a pixel and a light emitting device using a light emitting element represented by an electroluminescence (EL) element. A semiconductor device includes a circuit for performing processing for inputting video signals to pixels arranged in a display device to display an image. Here, more particularly, the semiconductor device includes a pulse output circuit represented by a shift register circuit, a latch circuit, a buffer circuit, a level shift circuit, or the like, or an amplifying circuit represented by an amplifier or the like.
2. Description of the Related Art
Display devices manufactured by forming semiconductor thin films on an insulator such as a glass substrate, in particular active matrix display devices represented by LCDs (liquid crystal displays) using thin film transistors (hereinafter referred to as TFTs) are being utilized in many manufactured products in recent years, and are spreading. The active matrix display devices using TFTs have from several hundred thousand to several million pixels arranged in a matrix shape, and display of an image is performed by controlling an electric charge of each pixel by TFTs disposed in each pixel.
In addition, techniques relating to polysilicon TFTs in which TFTs are used for a peripheral region of a pixel portion in addition to pixel TFTs constituting pixels to thereby form a driver circuit and the pixel portion on a substrate at the same time have also been developed recently. This contributes greatly to a reduction of the device in size and to a reduction of electric power consumption, and accordingly the display devices have come to be indispensable devices which are used in display portions of mobile information terminals and the like, whose fields of application have expanded remarkably in recent years.
In general, CMOS circuits in which N-channel TFTs and P-channel TFTs are combined are used as circuits for structuring semiconductor devices. However, the CMOS circuits require complex manufacturing processes, which leads to an increase in manufacturing cost and to a decrease in yield.
If all TFTs which compose the semiconductor device and the pixel portion can be produced to be unipolar, a part of the steps of adding an impurity element to a semiconductor layer can be omitted. Thus, the above problem can be solved.
Here, FIG. 10 shows a configuration of a source signal line driver circuit in a digital video input type display device as an example of a general semiconductor device. The source signal line driver circuit includes a shift register 1000 having plural stages of pulse output circuits 1001 for outputting a sampling pulse in succession in accordance with a clock signal (S-CK), a clock inverting signal (S-CKb), and a start pulse (SP), first latch circuits 1002 for holding 3 bits of digital video signals (Data1 to Data3) in accordance with an input of the sampling pulse, second latch circuits 1003 for holding the digital video signals in accordance with an input of a latch pulse (Latch Pulse), and D/A converting circuits 1004 for converting the digital video signals into analog video signals. Although not shown particularly, the driver circuit may include a buffer and the like. In addition, it is needless to say that the number of bits of the digital video signals is not limited to 3 bits.
The operation will be described briefly. The shift register 1000 outputs the sampling pulse in succession in accordance with inputs of the clock signal and the start pulse. The first latch circuits 1002 hold the digital video signals (Data1 to Data3) in response to timing when the sampling pulse is inputted thereto. After such an operation is conducted for one horizontal period, the latch pulse (Latch Pulse) is inputted to the second latch circuits 1003 during a horizontal retrace period. Thus, all of the digital video signals corresponding to one horizontal period which are held in the first latch circuits 1002 are transferred to the second latch circuits 1003. After that, the digital video signals are inputted to the D/A converting circuits 1004, converted into voltage signals corresponding to respective gray scales, and supplied to source signal lines (S0001 to S(final)).
The case where such a driver circuit is composed of unipolar TFTs will be described.
FIG. 5A shows a shift register composed of unipolar TFTs. The shift resistor includes plural stages of pulse output circuits 500 for outputting the sampling pulse in accordance with the clock signal and the start pulse. FIG. 5B is a circuit diagram of a single pulse output circuit. When a logic circuit is composed of unipolar TFTs, for example, N-channel TFTs, there is a problem in that an amplitude of an output signal is reduced as compared with that of an input signal by a threshold value of an N-channel TFT connected with a high potential side terminal of a power source. The pulse output circuit shown here solves such a problem by a bootstrap method and has been applied with Japanese Patent Application No. 2001-141347 by the same inventor(s) et al.
The operation of the circuit shown in FIG. 5B will be described briefly. Here, the unipolar TFTs composing the circuit are assumed to be N-channel TFTs and respective threshold voltages are assumed to be uniformly VthN. However, in a configuration of the circuit, it is not limited to an N-channel type.
The operation will be described. Note that there is the case where the operation of TFTs is described while the operation of the circuit is described. Here, the followings are assumed. When a TEF is turned ON, an absolute value of a voltage between the gate and the source of the TFT exceeds that of a threshold voltage of the TFT, so that an electrical connection state is obtained between the source region and the drain region of the TFT through the channel formation region. In addition, when a TFT is turned OFF, an absolute value of a voltage between the gate and the source of the TFT falls below that of a threshold voltage of the TFT, so that a non-electrical connection state is obtained between the source region and the drain region of the TFT.
Also, in order to describe a connection relationship of TFTs in this specification, the case of indicating terms “a gate electrode, an input electrode, and an output electrode” and the case of indicating terms “a gate electrode, a source region, and a drain region” are separately used. When the operation of the TFT is described, a voltage between the gate and the source is considered in many cases. However, it is difficult to make a positive distinction between the source region and the drain region of the TFT from the viewpoint of the structure thereof. Thus, when the input and output of a signal are described, they are called the input electrode and the output electrode. On the other hand, when a relationship of potentials in electrodes of the TFT is described, any one of the input electrode and the output electrode is called the source region and the other is called the drain region.
Further, amplitudes of signals in the description are assumed to be in a range of VDD to VSS, a high potential of a power source is given by VDD, and a low potential of the power source is given by VSS. In addition, it is assumed that VthN<(VDD−VthN) is satisfied. In order to simplify a relationship among respective potentials, it is considered to be VSS=0 V. However, when the circuit is actually operated, it is not limited to this.
In an m-th stage (1<m≦n) of pulse output circuit, when an (m−1)-th stage of output pulse is inputted to the gate electrodes of TFTs 501 and 504 (in the case of m=1, that is, in the case of the first stage, the start pulse SP is inputted thereto), the gate electrodes become an H (high) level so that the TFTs 501 and 504 are turned ON. Thus, a potential of the gate electrode of a TFT 505 is risen toward the VDD side. Then, when the potential reaches (VDD−VthN), the TFT 501 is turned OFF to obtain a floating state (where VthN<(VDD−VthN)). Therefore, the TFT 505 is turned ON. On the other hand, a pulse is not inputted to the gate electrodes of TFTs 502 and 503 at this time, thereby keeping the gate electrode in an L (low) level so that they are in an OFF state. Thus, a potential of the gate electrode of a TFT 506 is an L level so that it is in an OFF state. Therefore, when the clock signal CK inputted from the input electrode of the TFT 505 becomes an H level, a potential of an output terminal (SR Out) is risen toward the VDD side.
Here, a capacitor means 507 is provided between the gate electrode and the output electrode of the TFT 505. In addition, at this time, the gate electrode of the TFT 505 is in a floating state. Thus, a potential of the gate electrode of the TFT 505 is further risen from (VDD−VthN) by a bootstrap with rising a potential of the output terminal (SR Out). As a result, the potential of the gate electrode of the TFT 505 becomes a higher potential than (VDD+VthN). Accordingly, the potential of the output terminal (SR Out) is completely risen to VDD without reducing the potential by a threshold value of the TFT 505.
Similarly, in the case of a (m+1)-th stage, a pulse is outputted in accordance with the clock inverting signal S-CKb. An (m+1)-th stage of output pulse is fed back to the m-th stage and inputted to the gate electrodes of the TFTs 502 and 503. Thus, the gate electrodes of the TFTs 502 and 503 become in an H level so that they are turned ON. As a result, the potential of the gate electrode of the TFT 505 is fallen toward the VSS side and then the TFT 505 is turned OFF. Simultaneously, the potential of the gate electrode of the TFT 506 becomes an H level so that it is turned ON. Thus, the potential of the output terminal (SR Out) of the m-th stage becomes an L level.
Next, an example in which a latch circuit is composed of unipolar TFTs is shown in FIG. 6A. A circuit indicated by a dotted frame 601 corresponds to a first latch circuit and a circuit indicated by a dotted from 602 corresponds to a second latch circuit. A circuit indicated by a dotted frame 603 corresponds to a buffer circuit and is also shown in FIG. 6B. Note that a configuration of the buffer circuit 603 has been applied with Japanese Patent Application No. 2001-133431 by the same inventor(s) et al.
The first latch circuit 601 has a TFT 604 and a capacitor means 605. The digital video signal (Data) of 1 bit is inputted to the input electrode of the TFT 604 and a sampling pulse (Samp. Pulse) is inputted to the gate electrode thereof. When the sampling pulse is inputted, the TFT 604 is turned ON and the digital video signal is held in the capacitor means 605.
The second latch circuit 602 has a TFT 606 and a capacitor means 607. The digital video signal held in the first latch circuit is inputted to the input electrode of the TFT 606 and a latch pulse (Latch Pulse) is inputted to the gate electrode thereof. When the latch pulse is inputted, the TFT 606 is turned ON and the digital video signal is held in the capacitor means 607.
The buffer 603 has TFTs 608 to 611 and a capacitor means 612. The digital video signal held in the second latch circuit is inputted to the gate electrodes of the TFTs 609 and 611. The gate electrode of the TFT 608 is connected with the power source (VDD). Note that, it is constructed such that current power of the TFT 609 is sufficiently larger than that of the TFT 608.
When a signal having an H level is inputted to the gate electrodes of the TFTs 609 and 611, a potential of the gate electrode of the TFT 610 becomes an L level so that the TFT 610 is turned OFF. In addition, the TFT 611 is turned ON so that an L level is produced in an output terminal (Out).
When a signal having an L level is inputted to the gate electrodes of the TFTs 609 and 611, both TFTs 609 and 611 are turned OFF. Thus, the potential of the gate electrode of the TFT 610 is risen through the TFT 608. Then, when the potential reaches (VDD−VthN), a floating state is obtained. Thus, the TFT 610 is turned ON and a potential of the output terminal (Out) is risen. With rising, the potential of the gate electrode of the TFT 610 is further risen by the capacitor means 612, that is, capacitive coupling between the gate electrode and the output electrode of the TFT 610 and becomes higher than (VDD+VthN). As a result, an H level is produced in the output terminal (Out) and the potential thereof becomes equal to VDD.
Note that the buffer may be located between the first latch circuit 601 and the second latch circuit 602.
Here, the buffer 603 operated in response to the output of the second latch circuit is noted. During a period for which the TFT 609 is in an ON state after a signal having an H level is inputted to the TFT 609, a current path is produced through VDD, TFT 608, TFT 609, and VSS. Through the current path, a current continues to flow during a period for which a signal having an H level is outputted from the second latch circuit. In other words, when a digital video signal inputted to a latch circuit is an H level, a current continues to flow for one horizontal period in maximum. Thus, a dramatic increase in a consumption current is caused.